Continued growth in the capacity of dynamic random access memory (DRAM) technology can be enhanced by minimizing the size of individual DRAM cells. As technology develops, DRAM devices need to store more bits of information, use less power per bit of stored information and have the individual memory cells containing the stored bits occupy less area on the semiconductor chip. Furthermore, it is desirable to simplify the manufacturing process for DRAM devices, and thereby lower the cost of such devices. Each cell in such a device typically comprises a MOS pass transistor and a storage node forming one plate of a storage capacitor.
In order to simplify the manufacturing process and minimize the cell size of DRAM cells, there are three requirements which should be simultaneously satisfied. These include the simultaneous formation of the storage node contacts, the bit line contacts, and the contacts in the periphery circuit; the formation of the bit lines in a straight line configuration; and the use of the bit lines as wiring for the periphery circuits.
It has proven difficult to meet the requirement of simultaneous formation of the storage node, bit line and periphery circuit contacts by simple simultaneous formation of these contacts. An inward portion of the storage node contact is normally formed of either n-type or p-type doped polysilicon. This is due to the fact that employing metal in these locations is generally not desirable, since it would reduce the data retention time on the storage node, which would in turn require more frequent refreshing for the DRAM. Conversely to the situation for the storage node contacts, the contacts for the periphery circuit generally do require metal at inward portions, in order to form ohmic contacts for both n-type and p-type active regions. Doped polysilicon normally cannot be employed in this application.
Reference should now be had to FIGS. 1, 2 and 3. FIG. 1 shows a top plan view of a prior art DRAM device, while FIG. 2 shows a cross section taken along line II--II in FIG. 1 and FIG. 3 shows a cross section taken along line III--III in FIG. 1. The prior art device is designated generally as 10. It includes a plurality of word lines 12 and a plurality of bit lines 14. Also included are a plurality of storage nodes 16 and a plurality of active regions 18. A first type of contact is designated as 20 and a second type of contact is designated as 22. With particular reference to FIGS. 2 and 3, storage node 16 is interconnected to active region 18 through the second type of contact 22, an intermediate polysilicon pad 24, and the first type of contact 20. Similarly, bit line 14 is interconnected to active region 18 through the second type of contact 22, intermediate polysilicon pad 24, and the first type of contact 20. Isolators 26 are also shown in FIGS. 2 and 3. Note that a cell over bit line (COB) type of device is shown in the figures.
The prior art device shown in FIGS. 1-3 is subject to several problems. First, extra manufacturing steps are required. For example, an additional photolithography process is required for the formation of the first type of contact 20 and the pad 24. Additional deposition and etching processes are also required in conjunction with the photolithography process. Thus, manufacturing cost is increased. Further, the height of the second type of contact 22 from the substrate on which the active region 18 is formed to the bit lines 14 (which are also used as wiring in the periphery circuits) is increased due to the additional thickness needed for the first type of contact 20 and the polysilicon pad 24. This has caused difficulty in forming good ohmic contacts, that is, the second type of contact 22, in the periphery circuits.
Another prior device is disclosed in the article by Y. Kohyama et al. entitled "A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1 Gbit DRAM and Beyond," 1997 Symposium on VLSI Technology Digest of Technical Papers 17. This device employs polysilicon plugs with a so-called "Gate SAC" mask. The masked regions are identical in size and shape to the active areas. There is no provision for having a reduced contact diameter so as to prevent misalignment between the contacts (for the storage nodes, e.g.) and the polysilicon plugs, nor is there provision to prevent shorting together of some of the plugs due to alignment errors during photolithography.